If this file name was /bin/make, then the recipe executed is cd subdir. The error that you've quoted must have been preceded by an error from gcc, please quote that as well. The definition is accessible inside the makefile.
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Can i pass variables to a gnu makefile as command line arguments? In other words, i want to pass some arguments which will eventually become variables in the makefile. What's the difference between them?
Cd subdir && $(make) the value of this variable is the file name with which make was invoked.
+ i was not familar. By using 'gmake' specifically you can use gnu make extensions. The language accepted by gnu make is a superset of the one supported by the traditional make utility. Msys2 have many types of runtime and they.
I want to use the make command as part of setting up the code environment, but i'm using windows. For variable assignment in make, i see := and = operator. I usually pass macro definitions from make command line to a makefile using the option:
