In other words, i want to pass some arguments which will eventually become variables in the makefile. The language accepted by gnu make is a superset of the one supported by the traditional make utility. The definition is accessible inside the makefile.
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Cd subdir && $(make) the value of this variable is the file name with which make was invoked. The error that you've quoted must have been preceded by an error from gcc, please quote that as well. What's the difference between them?
For variable assignment in make, i see := and = operator.
By using 'gmake' specifically you can use gnu make extensions. + i was not familar. If this file name was /bin/make, then the recipe executed is cd subdir. Msys2 have many types of runtime and they.
Can i pass variables to a gnu makefile as command line arguments? I usually pass macro definitions from make command line to a makefile using the option: I want to use the make command as part of setting up the code environment, but i'm using windows.
